The present invention relates, in general, to the field of integrated circuit devices. More particularly, the present invention relates to a circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices such as, for example, double data rate synchronous dynamic random access memories (DDR SDRAMs).
It has become increasingly important in digital circuits that an accurate 50% duty cycle clock be generated since actions are taken on both the rising and falling edges of the clock. The use of a dual slope integrator scheme to indicate when a signal has a 50% duty cycle is known in the art. This scheme utilizes two current sources of equal magnitude, one to charge an integrating capacitor when the signal is “high” and the other to discharge the capacitor when the signal is “low”. When the signal has a 50% duty cycle, there will be no net charge transferred to the capacitor during a clock cycle and the voltage on the capacitor will stabilize.
When the signal has a duty cycle greater than 50%, the voltage on the capacitor will increase. When the duty cycle is less than 50%, the voltage on the capacitor will decrease. The voltage on the capacitor can, in turn, be used to control the duty cycle; i.e., a “control voltage” is generated. In some cases, two control voltages have been generated, one utilizing the clock and one using the complement of the clock. In this case, the two control voltages move in opposite directions as the duty cycle diverges from 50%.
A number of different techniques have been proposed for using the above described control voltage to adjust the duty cycle. It is also known that using the same technique with current sources that are not equal can be used to generate signals with precise duty cycles other than 50%. Examples of the above listed techniques are described, for example, in U.S. Pat. Nos. 7,015,739; 6,781,419 and 6, 975, 100.
The duty cycle deviation is the result of the rising and falling edges of a 50% duty cycle input signal propagating at different rates through the circuitry intervening between the input and a point at which the propagated signal is used. A common approach used for adjusting the duty cycle is to add voltage-controlled duty cycle adjusting circuitry to the intervening path. The added duty cycle adjusting circuitry in this approach uses the control voltage(s) to cause the rising and falling edge propagation delays to differ in opposite directions to those of the circuitry between the input and the added duty cycle adjusting circuitry. Thus, the duty cycle is adjusted toward the desired value.
In U.S. Pat. No. 6,781,419 in particular, a voltage-controlled inverter is used to adjust the output slew rates of the rising and falling edges in opposite directions thus adjusting the duty cycle. A voltage-controlled current regulating P-channel transistor is used to control the inverter output rising edge slew rate. An N-channel voltage-controlled regulating transistor is used to control the inverter output falling edge slew rate. The control voltages used to control the P-channel and N-channel transistors are derived from the voltage generated by a dual slope integrator as described above rather than using this voltage directly.
The use of both P-channel and N-channel current regulation transistors in voltage-controlled inverters presents a problem in that both transistors require low threshold voltages if a dual slope integrator is to be used directly as the control voltage. Further, the control voltage generated using a dual slope integrator is conventionally not used directly. Rather, control voltages are derived from this voltage thus necessitating additional circuit complexity.